1. Field of the Invention
The present invention relates to circuits for processing a clock signal in a digital circuit. Specifically, the present invention relates to circuit techniques suitable for correction of the duty cycle of a clock signal produced by a frequency divider circuit or the like.
2. Description of the Related Art
For digital circuits, it is of great importance to keep a clock signal, which is used for synchronizing the operations of various units in the circuit, in a 50% duty cycle. Generally, a clock signal with a 50% duty cycle is produced by a frequency divider circuit.
FIG. 7 shows a typical circuit configuration of the frequency divider circuit (a divide-by-two frequency divider circuit). A frequency divider circuit 100 shown in FIG. 7 receives a clock signal CK0 and divides by two the frequency thereof to output a resulting clock signal CK1. By dividing by two the frequency of the clock signal CK0, both the periods of time for which the clock signal CK1 has the logic values “H” and “L” can be set at the period of time equivalent to one cycle of the clock signal CK0. Thereby this circuit provides the clock signal CK1 reaching a duty cycle of approximately 50% (See, for example, Document 1: William J. Dally, et al., “Digital Systems Engineering” (USA) Cambridge University Press, pp.581 (August 1998)).
In recent years, digital circuits have employed clock signals of very high frequency. With such trend, it becomes difficult to provide a clock signal with a 50% duty cycle because of the effect of signal propagation delay caused by transistors constituting the frequency divider circuit 100, especially the effect of delay caused by the MOS resistances. This difficulty will be described below.
FIG. 8 illustrates how a signal is propagated in the case where the logic value of the clock signal CK1 output by the frequency divider circuit 100 changes. FIG. 8A illustrates how a signal is propagated where the clock signal CK1 rises (“L”→“H”). FIG. 8B illustrates how a signal is propagated where the clock signal CK1 falls (“H”→“L”).
In a dynamic divide-by-two frequency divider circuit such as the frequency divider circuit 100, the logic value of the clock signal CK1 changes in response to the rising of the clock signal CK0. Signal propagation delay occurring when the clock signal CK1 rises results from the turn-ons of an n-channel transistor 101 and a p-channel transistor 102. On the other hand, signal propagation delay occurring when the clock signal CK1 falls results from the turn-on of an n-channel transistor 103. Consequently, the rising of the clock signal CK1 causes an extra delay by an amount equivalent to one p-channel transistor as compared to the falling of the clock signal CK1.
FIG. 9 shows waveforms of the clock signals CK0 and CK1 as an input and output of the frequency divider circuit 100, respectively. A delay d1 of the rising of the clock signal CK1 relative to the rising of the clock signal CK0 occurring in a regular cycle is greater than a delay d2 of the falling of the clock signal CK1, so that the duty cycle of the clock signal CK1 is deviated by an error d3 from the timing of a 50% duty cycle. If the clock signals CK0 and CK1 have relatively low frequencies, the error d3 can be neglected. However, as the frequencies thereof become higher, the error d3 cannot be neglected.